1. Field of the Invention
The present invention involves fabrication of semiconductor devices using Silicon-on-Insulator (SOI) technology. More specifically the invention is directed to the use of the SOI Buried Oxide (BOX) layer as an integral component of electronic devices and circuits.
2. Description of the Related Art
Silicon-On-Insulator (SOI) technology has emerged as an electronic fabrication technique that improves characteristics such as latch-up and speed, although typically at higher manufacturing cost. The term SOI typically describes structures where devices are fabricated in single-crystal Si layers formed over an insulating film or substrate.
FIGS. 11A and 11B show a typical conventional SOI structure, where a thin silicon device layer 110 formed on an insulator 111 is supported over substrate 112. For current technology the substrate is most commonly silicon and the insulator is most commonly silicon dioxide. Devices 113 are formed in device layer 110 and interconnected by surface conductors 114. The conventional SOI structure is predominantly created by one of two techniques.
The first process, known as SIMOX (Separation by IMplanted OXygen), consists of implantation of oxygen into an Si substrate at a prescribed depth and heating it to form a continuous layer of SiO2. The SIMOX process requires only a single wafer. The alternate process, shown in greater detail later, is commonly referred to as “Bonded SOI” and starts with two wafers, preferably with at least one having an oxide surface. The first wafer is the carrier wafer which is joined together with the second wafer, and the second wafer is “thinned” to leave a layer of silicon bonded onto the carrier wafer, separated by an insulator layer.
Both of the techniques have experienced many variations and enhancements over the years for improvement of yield and lower cost and to achieve desirable device layer quality for uniformity and defects. An important characteristic of conventional SOI that is obvious from FIG. 11B is that the insulator layer 111 is used primarily for isolating the silicon device layer 110 with its active devices 113 from the silicon substrate 112. Thus, the conventional wisdom forms devices on the device layer 110 on only one side of the insulator layer 111.
The problem with this approach is that, although devices and interconnects are formed similar to conventional substrates, SOI techniques introduce newer problems such as floating body effects. Additionally, conventional SOI structure takes up considerably more chip “real estate” than required in corresponding non-SOI structure, since floating body effects which not an issue with conventional substrates require additional connections to the channel regions. There are also added process steps to provide ground interconnections to the substrate. More important, the conventional approach fails to recognize that the insulator layer could provide more functionality than merely separating predetermined groups of devices from the substrate.